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www.latticesemi.com 1 ds1022_01.4 ispmach 4000ze family 1.8v in-system programmable ultra low power plds may 2009 data sheet ds1022 ?2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. features high performance ? max = 260mhz maximum operating frequency ? pd = 4.4ns propagation delay up to four global clock pins with programmable clock polarity control up to 80 pts per output ease of design flexible cpld macrocells with individual clock, reset, preset and clock enable controls up to four global oe controls individual local oe control per i/o pin excellent first-time-fit tm and re? wide input gating (36 input logic blocks) for fast counters, state machines and address decoders ultra low power standby current as low as 10? typical 1.8v core; low dynamic power operational down to 1.6v v cc superior solution for power sensitive consumer applications per pin pull-up, pull-down or bus keeper control * power guard with multiple enable signals* broad device offering 32 to 256 macrocells multiple temperature range support ?commercial: 0 to 90? junction (t j ) ?industrial: -40 to 105? junction (t j ) space-saving ucbga and csbga packages* easy system integration operation with 3.3v, 2.5v, 1.8v or 1.5v lvcmos i/o 5v tolerant i/o for lvcmos 3.3, lvttl, and pci interfaces hot-socketing support open-drain output option programmable output slew rate 3.3v pci compatible i/o pins with fast setup path input hysteresis* 1.8v core power supply ieee 1149.1 boundary scan testable ieee 1532 isc compliant 1.8v in-system programmable (isp) using boundary scan test access port (tap) pb-free package options (only) on-chip user oscillator and timer* *new enhanced features over original ispmach 4000z table 1. ispmach 4000ze family selection guide ispmach 4032ze ispmach 4064ze ispmach 4128ze ispmach 4256ze macrocells 32 64 128 256 t pd (ns) 4.4 4.7 5.8 5.8 t s (ns) 2.2 2.5 2.9 2.9 t co (ns) 3.0 3.2 3.8 3.8 f max (mhz) 260 241 200 200 supply voltages (v) 1.8v 1.8v 1.8v 1.8v packages 1 (i/o + dedicated inputs) 48-pin tqfp (7 x 7mm) 32+4 32+4 64-ball csbga (5 x 5mm) 32+4 48+4 64-ball ucbga (4 x 4mm) 48+4 100-pin tqfp (14 x 14mm) 64+10 64+10 64+10 132-ball ucbga (6 x 6mm) 96+4 144-pin tqfp (20 x 20mm) 96+4 96+14 144-ball csbga (7 x 7mm) 64+10 96+4 108+4 1. pb-free only.
lattice semiconductor ispmach 4000ze family data sheet 2 introduction the high performance ispmach 4000ze family from lattice offers an ultra low power cpld solution. the new fam- ily is based on lattices industry-leading ispmach 4000 architecture. retaining the best of the previous generation, the ispmach 4000ze architecture focuses on signi?ant innovations to combine high performance with low power in a ?xible cpld family. for example, the familys new power guard feature minimizes dynamic power consump- tion by preventing internal logic toggling due to unnecessary i/o pin activity. the ispmach 4000ze combines high speed and low power with the ?xibility needed for ease of design. with its robust global routing pool and output routing pool, this family delivers excellent first-time-fit, timing predictabil- ity, routing, pin-out retention and density migration. the ispmach 4000ze family offers densities ranging from 32 to 256 macrocells. there are multiple density-i/o combinations in thin quad flat pack (tqfp), chip scale bga (csbga), and ultra chip scale bga (ucbga) pack- ages ranging from 32 to 144 pins/balls. table 1 shows the macrocell, package and i/o options, along with other key parameters. a user programmable internal oscillator and a timer are included in the device for tasks like led control, keyboard scanner and similar housekeeping type state machines. this feature can be optionally disabled to save power. the ispmach 4000ze family has enhanced system integration capabilities. it supports a 1.8v supply voltage and 3.3v, 2.5v, 1.8v and 1.5v interface voltages. additionally, inputs can be safely driven up to 5.5v when an i/o bank is con?ured for 3.3v operation, making this family 5v tolerant. the ispmach 4000ze also offers enhanced i/o features such as slew rate control, pci compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. pull-up, pull-down and bus-keeper features are controllable on a ?er-pin basis. the ispmach 4000ze family members are 1.8v in-system programmable through the ieee standard 1532 interface. ieee standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. the 1532 interface signals tck, tms, tdi and tdo are referenced to v cc (logic core). overview the ispmach 4000ze devices consist of multiple 36-input, 16-macrocell generic logic blocks (glbs) intercon- nected by a global routing pool (grp). output routing pools (orps) connect the glbs to the i/o blocks (iobs), which contain multiple i/o cells. this architecture is shown in figure 1. figure 1. functional block diagram i/o block orp orp 16 osc 16 goe0 goe1 v cc gnd tck tms tdi tdo 36 generic logic block generic logic block i/o block orp orp 16 36 generic logic block generic logic block i/o block i/o bank 0 i/o bank 1 i/o block 36 36 clk0/i clk1/i clk2/i clk3/i 16 16 global routing pool v cco0 gnd v cco1 gnd 16 16 16
lattice semiconductor ispmach 4000ze family data sheet 3 the i/os in the ispmach 4000ze are split into two banks. each bank has a separate i/o power supply. inputs can support a variety of standards independent of the chip or bank power supply. outputs support the standards com- patible with the power supply provided to the bank. support for a variety of standards helps designers implement designs in mixed voltage environments. in addition, 5v tolerant inputs are speci?d within an i/o bank that is con- nected to a v cco of 3.0v to 3.6v for lvcmos 3.3, lvttl and pci interfaces. architecture there are a total of two glbs in the ispmach 4032ze, increasing to 16 glbs in the ispmach 4256ze. each glb has 36 inputs. all glb inputs come from the grp and all outputs from the glb are brought back into the grp to be connected to the inputs of any other glb on the device. even if feedback signals return to the same glb, they still must go through the grp. this mechanism ensures that glbs communicate with each other with consistent and predictable delays. the outputs from the glb are also sent to the orp. the orp then sends them to the asso- ciated i/o cells in the i/o block. generic logic block the ispmach 4000ze glb consists of a programmable and array, logic allocator, 16 macrocells and a glb clock generator. macrocells are decoupled from the product terms through the logic allocator and the i/o pins are decou- pled from macrocells through the orp. figure 2 illustrates the glb. figure 2. generic logic block and array the programmable and array consists of 36 inputs and 83 output product terms. the 36 inputs from the grp are used to form 72 lines in the and array (true and complement of the inputs). each line in the array can be con- nected to any of the 83 output product terms via a wired-and. each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the shared pt clock, shared pt initialization and shared pt oe. the shared pt clock and shared pt initialization signals can optionally be inverted before being fed to the macrocells. every set of ?e product terms from the 80 logic product terms forms a product term cluster starting with pt0. there is one product term cluster for every macrocell in the glb. figure 3 is a graphical representation of the and array. logic allocator 36 inputs from grp 16 macrocells to orp to grp to product term output enable sharing. also, to input enable of power guard on i/os in the block. 1+oe 16 mc feedback signals clock generator 1+oe 1+oe 1+oe 1+oe 1+oe 1+oe clk0 clk1 clk2 clk3 1+oe and array 36 inputs, 83 product terms
lattice semiconductor ispmach 4000ze family data sheet 4 figure 3. and array enhanced logic allocator within the logic allocator, product terms are allocated to macrocells in product term clusters. each product term cluster is associated with a macrocell. the cluster size for the ispmach 4000ze family is 4+1 (total 5) product terms. the software automatically considers the availability and distribution of product term clusters as it ?s the functions within a glb. the logic allocator is designed to provide two speed paths: 20-pt speed locking path and an up to 80-pt path. the availability of these two paths lets designers trade timing variability for increased perfor- mance. the enhanced logic allocator of the ispmach 4000ze family consists of the following blocks: product term allocator cluster allocator wide steering logic figure 4 shows a macrocell slice of the logic allocator. there are 16 such slices in the glb. figure 4. macrocell slice pt0 pt1 cluster 0 pt2 pt3 pt4 in[0] in[34] in[35] note: indicates programmable fuse. pt80 pt81 pt82 shared pt clock shared pt initialization shared ptoe/bie pt76 pt77 pt78 pt79 pt75 cluster 15 to n +1 to n -1 to n -2 from n -1 from n -4 from n +2 from n +1 5-pt from n -4 1-80 pts to n +4 to xor (mc) cluster individual product term allocator cluster allocator superwide steering logic n
lattice semiconductor ispmach 4000ze family data sheet 5 product term allocator the product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. product terms that are used as logic are steered into a 5-input or gate associ- ated with the cluster. product terms that used for control are steered either to the macrocell or i/o cell associated with the cluster. table 2 shows the available functions for each of the ?e product terms in the cluster. table 2. individual pt steering cluster allocator the cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions with more product terms. table 3 shows which clusters can be steered to which macrocells. used in this manner, the cluster allocator can be used to form functions of up to 20 product terms. additionally, the cluster allocator accepts inputs from the wide steering logic. using these inputs, functions up to 80 product terms can be created. table 3. available clusters for each macrocell wide steering logic the wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca- tor n +4. thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions and allowing performance to be increased through a single glb implementation. table 4 shows the product term chains. product term logic control pt n logic pt single pt for xor/or pt n +1 logic pt individual clock (pt clock) pt n +2 logic pt individual initialization or individual clock enable (pt initialization/ce) pt n +3 logic pt individual initialization (pt initialization) pt n +4 logic pt individual oe (ptoe) macrocell available clusters m0 c0c1c2 m1 c0 c1 c2 c3 m2 c1 c2 c3 c4 m3 c2 c3 c4 c5 m4 c3 c4 c5 c6 m5 c4 c5 c6 c7 m6 c5 c6 c7 c8 m7 c6 c7 c8 c9 m8 c7 c8 c9 c10 m9 c8 c9 c10 c11 m10 c9 c10 c11 c12 m11 c10 c11 c12 c13 m12 c11 c12 c13 c14 m13 c12 c13 c14 c15 m14 c13 c14 c15 m15 c14 c15
lattice semiconductor ispmach 4000ze family data sheet 6 table 4. product term expansion capability every time the super cluster allocator is used, there is an incremental delay of t exp . when the super cluster alloca- tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus- ter is steered to m (n+4), then m (n) is ground). macrocell the 16 macrocells in the glb are driven by the 16 outputs from the logic allocator. each macrocell contains a pro- grammable xor gate, a programmable register/latch, along with routing for the logic and control functions. figure 5 shows a graphical representation of the macrocell. the macrocells feed the orp and grp. a direct input from the i/o cell allows designers to use the macrocell to construct high-speed input registers. a programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. figure 5. macrocell enhanced clock multiplexer the clock input to the ?p-?p can select any of the four block clocks along with the shared pt clock, and true and complement forms of the optional individual term clock. an 8:1 multiplexer structure is used to select the clock. the eight sources for the clock multiplexer are as follows: block clk0 block clk1 expansion chains macrocells associated with expansion chain (with wrap around) max pt/ macrocell chain-0 m0 m4 m8 m12 m0 75 chain-1 m1 m5 m9 m13 m1 80 chain-2 m2 m6 m10 m14 m2 75 chain-3 m3 m7 m11 m15 m3 70 single pt block clk0 block clk1 block clk2 block clk3 pt clock (optional) shared pt clock ce d/t/l q rp shared pt initialization pt initialization/ce (optional) pt initialization (optional) from logic allocator power-up initialization to orp to grp from i/o cell delay
lattice semiconductor ispmach 4000ze family data sheet 7 block clk2 block clk3 pt clock pt clock inverted shared pt clock ground clock enable multiplexer each macrocell has a 4:1 clock enable multiplexer. this allows the clock enable signal to be selected from the fol- lowing four sources: pt initialization/ce pt initialization/ce inverted shared pt clock logic high initialization control the ispmach 4000ze family architecture accommodates both block-level and macrocell-level set and reset capa- bility. there is one block-level initialization term that is distributed to all macrocell registers in a glb. at the macro- cell level, two product terms can be ?tolen from the cluster associated with a macrocell to be used for set/reset functionality. a reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, pro- viding ?xibility. note that the reset/preset swapping selection feature affects power-up reset as well. all ?p-?ps power up to a known state for predictable system initialization. if a macrocell is con?ured to set on a signal from the block-level initialization, then that macrocell will be set during device power-up. if a macrocell is con?ured to reset on a signal from the block-level initialization or is not con?ured for set/reset, then that macrocell will reset on power- up. to guarantee initialization values, the v cc rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. glb clock generator each ispmach 4000ze device has up to four clock pins that are also routed to the grp to be used as inputs. these pins drive a clock generator in each glb, as shown in figure 6. the clock generator provides four clock sig- nals that can be used anywhere in the glb. these four glb clock signals can consist of a number of combinations of the true and complement edges of the global clock signals. figure 6. glb clock generator clk0 clk1 clk2 clk3 block clk0 block clk1 block clk2 block clk3
lattice semiconductor ispmach 4000ze family data sheet 8 output routing pool (orp) the output routing pool allows macrocell outputs to be connected to any of several i/o cells within an i/o block. this provides greater ?xibility in determining the pinout and allows design changes to occur without affecting the pinout. the output routing pool also provides a parallel capability for routing macrocell-level oe product terms. this allows the oe product term to follow the macrocell output as it is switched between i/o cells. the enhanced orp of the ispmach 4000ze family consists of the following elements: output routing multiplexers oe routing multiplexers figure 7 shows the structure of the orp from the i/o cell perspective. this is referred to as an orp slice. each orp has as many orp slices as there are i/o cells in the corresponding i/o block. figure 7. orp slice output routing multiplexers the details of connections between the macrocells and the i/o cells vary across devices and within a device dependent on the maximum number of i/os available. tables 5-7 provide the connection details. table 5. glb/mc/orp combinations for ispmach 4256ze glb/mc orp mux input macrocells [glb] [mc 0] m0, m1, m2, m3, m4, m5, m6, m7 [glb] [mc 1] m2, m3, m4, m5, m6, m7, m8, m9 [glb] [mc 2] m4, m5, m6, m7, m8, m9, m10, m11 [glb] [mc 3] m6, m7, m8, m9, m10, m11, m12, m13 [glb] [mc 4] m8, m9, m10, m11, m12, m13, m14, m15 [glb] [mc 5] m10, m11, m12, m13, m14, m15, m0, m1 [glb] [mc 6] m12, m13, m14, m15, m0, m1, m2, m3 [glb] [mc 7] m14, m15, m0, m1, m2, m3, m4, m5 output routing multiplexer oe routing multiplexer from macrocell from ptoe to i/o cell to i/o cell oe
lattice semiconductor ispmach 4000ze family data sheet 9 table 6. glb/mc/orp combinations for ispmach 4128ze table 7. glb/mc/orp combinations for ispmach 4032ze and 4064ze output enable routing multiplexers the oe routing pool provides the corresponding local output enable (oe) product term to the i/o cell. i/o cell the i/o cell contains the following programmable elements: output buffer, input buffer, oe multiplexer, power guard and bus maintenance circuitry. figure 8 details the i/o cell. glb/mc orp mux input macrocells [glb] [mc 0] m0, m1, m2, m3, m4, m5, m6, m7 [glb] [mc 1] m1, m2, m3, m4, m5, m6, m7, m8 [glb] [mc 2] m2, m3, m4, m5, m6, m7, m8, m9 [glb] [mc 3] m4, m5, m6, m7, m8, m9, m10, m11 [glb] [mc 4] m5, m6, m7, m8, m9, m10, m11, m12 [glb] [mc 5] m6, m7, m8, m9, m10, m11, m12, m13 [glb] [mc 6] m8, m9, m10, m11, m12, m13, m14, m15 [glb] [mc 7] m9, m10, m11, m12, m13, m14, m15, m0 [glb] [mc 8] m10, m11, m12, m13, m14, m15, m0, m1 [glb] [mc 9] m12, m13, m14, m15, m0, m1, m2, m3 [glb] [mc 10] m13, m14, m15, m0, m1, m2, m3, m4 [glb] [mc 11] m14, m15, m0, m1, m2, m3, m4, m5 glb/mc orp mux input macrocells [glb] [mc 0] m0, m1, m2, m3, m4, m5, m6, m7 [glb] [mc 1] m1, m2, m3, m4, m5, m6, m7, m8 [glb] [mc 2] m2, m3, m4, m5, m6, m7, m8, m9 [glb] [mc 3] m3, m4, m5, m6, m7, m8, m9, m10 [glb] [mc 4] m4, m5, m6, m7, m8, m9, m10, m11 [glb] [mc 5] m5, m6, m7, m8, m9, m10, m11, m12 [glb] [mc 6] m6, m7, m8, m9, m10, m11, m12, m13 [glb] [mc 7] m7, m8, m9, m10, m11, m12, m13, m14 [glb] [mc 8] m8, m9, m10, m11, m12, m13, m14, m15 [glb] [mc 9] m9, m10, m11, m12, m13, m14, m15, m0 [glb] [mc 10] m10, m11, m12, m13, m14, m15, m0, m1 [glb] [mc 11] m11, m12, m13, m14, m15, m0, m1, m2 [glb] [mc 12] m12, m13, m14, m15, m0, m1, m2, m3 [glb] [mc 13] m13, m14, m15, m0, m1, m2, m3, m4 [glb] [mc 14] m14, m15, m0, m1, m2, m3, m4, m5 [glb] [mc 15] m15, m0, m1, m2, m3, m4, m5, m6
lattice semiconductor ispmach 4000ze family data sheet 10 figure 8. i/o cell each output supports a variety of output standards dependent on the v cco supplied to its i/o bank. outputs can also be con?ured for open drain operation. each input can be programmed to support a variety of standards, inde- pendent of the v cco supplied to its i/o bank. the i/o standards supported are: lvttl lvcmos 1.8 lvcmos 3.3 lvcmos 1.5 lvcmos 2.5 3.3v pci compatible all of the i/os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down resistor selectable on a ?er-pin basis. a fourth option is to provide none of these. the default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is con?ured to be a pull-down resistor. each ispmach 4000ze device i/o has an individually programmable output slew rate control bit. each output can be individually con?ured for fast slew or slow slew. the typical edge rate difference between fast and slow slew setting is 20%. for high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re?ctions, less noise and keep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. the ispmach 4000ze family has an always on, 200mv typical hysteresis for each input operational at 3.3v and 2.5v. this provides improved noise immunity for slow transitioning signals. power guard power guard allows easier achievement of standby current in the system. as shown in figure 9, this feature con- sists of an enabling multiplexer between an i/o pin and input buffer, and its associated circuitry inside the device. if the enable signal (e) is held low, all inputs (d) can be optionally isolated (guarded), such that, if any of these were toggled, it would not cause any toggle on internal pins (q), thus, a toggling i/o pin will not cause any internal dynamic power consumption. to macrocell to grp vcco goe 0 goe 1 goe 2 goe 3 vcc from orp from orp 0 1 block input enable (bie) (from block pt) power guard disable fuse (pgdf) 0 1 power guard i/o bus maintenance vcco
lattice semiconductor ispmach 4000ze family data sheet 11 figure 9. power guard all the i/o pins in a block share a common power guard enable signal. for a block of i/os, this signal is called a block input enable (bie) signal. bie can be internally generated using mc logic, or could come from external sources using one of the user i/o or input pins. any i/o pin in the block can be programmed to ignore the bie signal. thus, the feature can be enabled or disabled on a pin-by-pin basis. figure 10 shows power guard and bie across multiple i/os in a block that has eight i/os. figure 10. power guard and bie in a block with 8 i/os 0 1 e q d power guard power guard to macrocell i/o 0 i/o 1 i/o 7 to grp 0 1 to macrocell to grp to macrocell to grp block inp u t ena b le (bie) from block pt. the block pt is part of the b lock a n d array, and can b e dri v en b y signals from the grp. power guard power guard 0 1 0 1
lattice semiconductor ispmach 4000ze family data sheet 12 the number of bie inputs, thus the number of power guard ?locks that can exist in a device, depends on the device size. table 8 shows the number of bie signals available in the ispmach 4000ze family. the number of i/os available in each block is shown in the ordering information section of this data sheet. table 8. number of bie signals available in ispmach 4000ze devices power guard for dedicated inputs power guard can optionally be applied to the dedicated inputs. the dedicated inputs and clocks are controlled by the bie of the logic blocks shown in tables 9 and 10. table 10. dedicated inputs to bie association for more information on the power guard function refer to tn1174, adv anced f eatures of the ispma ch 4000ze f amily . global oe (goe) and block input enable (bie) generation most ispmach 4000ze family devices have a 4-bit wide global oe (goe) bus (figure 11), except the ispmach 4032 device that has a 2-bit wide global oe bus (figure 12). this bus is derived from a 4-bit internal global oe (goe) pt bus and two dual purpose i/o or goe pins. each signal that drives the bus can optionally be inverted. each glb has a block-level oe pt that connects to all bits of the global oe pt bus with four fuses. hence, for a 256-macrocell device (with 16 blocks), each line of the bus is driven from 16 oe product terms. figures 9 and 10 show a graphical representation of the global oe generation. device number of logic blocks, power guard blocks and bie signals ispmach 4032ze two (blocks: a and b) ispmach 4064ze four (blocks: a, b, c and d) ispmach 4128ze eight (blocks: a, b, c, ? h) ispmach 4256ze sixteen (blocks: a, b, c, ? p) table 9. dedicated clock inputs to bie association clk/i 32 mc block 64mc block 128mc block 256mc block clk0 / i aaaa clk1 / i a b d h clk2 / i b c e i clk3 / i b d h p dedicated input 4064ze block 4128ze block 4256ze block 0abd 1bce 2bdg 3cfg 4dgj 5dhl 6m 7o 8o 9b
lattice semiconductor ispmach 4000ze family data sheet 13 the block-level oe pt of each glb is also tied to block input enable (bie) of that block. hence, for a 256-macro- cell device (with 16 blocks), each block's bie signal is driven by block-level oe pt from each block. figure 11. global oe generation for all devices except ispmach 4032ze figure 12. global oe generation for ispmach 4032ze on-chip oscillator and timer an internal oscillator is provided for use in miscellaneous housekeeping functions such as watchdog heartbeats, digital de-glitch circuits and control state machines. the oscillator is disabled by default to save power. figure 13 shows the block diagram of the oscillator and timer block. shared ptoe (block 0) shared ptoe (block n) bie0 bien global fuses goe (0:3) to i/o cells internal global oe pt bus (4 lines) 4-bit global oe bus global oe fuse connection hard wired shared ptoe (block 0) shared ptoe (block 1) global fuses goe (3:0) to i/o cells internal global oe pt bus (2 lines) 4-bit global oe bus global oe fuse connection hard wired bie0 bie1
lattice semiconductor ispmach 4000ze family data sheet 14 figure 13. on-chip oscillator and timer table 11. on-chip oscillator and timer signal names osctimer has two outputs, oscout and timerout. the outputs feed into the global routing pool (grp). from grp, these signals can drive any macrocell input, as well as any output pin (with macrocell bypass). the out- put oscout is the direct oscillator output with a typical frequency of 5mhz, whereas, the output timerout is the oscillator output divided by an attribute timer_div. the attribute timer_div can be: 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits). the divided output is provided for those user situations, where a very slow clock is desired. if even a slower toggling clock is desired, then the pro- grammable macrocell resources can be used to further divide down the timerout output. figure 14 shows the simpli?d relationship among oscout, timerres and timerout. in the diagram, the sig- nal ? is an internal reset signal that is used to synchronize timerres to oscout. this adds one extra clock cycle delay for the ?st timer transition after timerres. figure 14. relationship among oscout, timerres and timerout signal name input or out- put optional / required description oscout output optional oscillator output (nominal frequency: 5mhz) timerout output optional oscillator frequency divided by an integer timer_div (default 128) timerres input optional reset the timer dynoscdis input optional disables the oscillator, resets the timer and saves the power. osctimer oscout timerout timerres dynoscdis n ote: n = nu m b er of b its in the di v ider (7, 10 or 20) metasta b ility: if the signal timerres is not synchrono u s to oscout, it co u ld make a difference of one or t w o clock cycles to the timerout going high the first time. oscout 22 n / 2 2 n 1 0 -1 timerres timerout r (internal) mp w
lattice semiconductor ispmach 4000ze family data sheet 15 some simple use scenarios the following diagrams show a few simple examples that omit optional signals for the osctimer block: a. an oscillator giving 5mhz nominal clock b. an oscillator that can be disabled with an external signal (5mhz nominal clock) c. an oscillator giving approximately 5 hz nominal clock (timer_div = 2 20 (1,048,576)) d. an oscillator giving two output clocks: ~5mhz and ~5khz (timer_div= 2 10 (1,024)) osctimer integration with cpld fabric the osctimer is integrated into the cpld fabric using the global routing pool (grp). the macrocell (mc) feed- back path for two macrocells is augmented with a programmable multiplexer, as shown in figure 15. the osc- timer outputs (oscout and timerout) can optionally drive the grp lines, whereas the macrocell outputs can drive the optional osctimer inputs timerres and dynoscdis. figure 15. osctimer integration with cpld fabric table 12 shows how these two mcs are designated in each of the ispmach4000ze device. osctime r ti me r_div= n /a oscout (a) a simple 5mhz oscillator. (b) an oscillator with dynamic disable. (d) oscillator with two outputs (5mhz and 5khz). (c) a simple 5hz oscillator. dynos cdis osctime r ti me r_div= n /a oscout osctime r ti me r_div= 2 20 timerout osctime r ti me r_div= 2 10 oscout timerout 1 0 1 0 1 0 1 0 a regular macrocell osc macrocell timer macrocell to grp to grp to grp macrocell feedback signal macrocell 15 feedback signal oscout dynoscdis timerout timerres macrocell 15 feedback signal
lattice semiconductor ispmach 4000ze family data sheet 16 table 12. osc and timer mc designation zero power/low power and power management the ispmach 4000ze family is designed with high speed low power design techniques to offer both high speed and low power. with an advanced e 2 low power cell and non sense-ampli?r design approach (full cmos logic approach), the ispmach 4000ze family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without needing any ?urbo bits or other power management schemes associated with a traditional sense- ampli?r approach. the zero power ispmach 4000ze is based on the 1.8v ispmach 4000z family. with innovative circuit design changes, the ispmach 4000ze family is able to achieve the industrys lowest static power. ieee 1149.1-compliant boundary scan testability all ispmach 4000ze devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri?ation. in addition, these devices can be linked into a board-level serial scan path for more board-level testing. the test access port operates with an lvcmos interface that corresponds to the power supply voltage. i/o quick con?uration to facilitate the most ef?ient board test, the physical nature of the i/o cells must be set before running any continu- ity tests. as these tests are fast, by nature, the overhead and time that is required for con?uration of the i/os physical nature should be minimal so that board test time is minimized. the ispmach 4000ze family of devices allows this by offering the user the ability to quickly con?ure the physical nature of the i/o cells. this quick con?- uration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. lattice's ispvm system programming software can either perform the quick con?uration through the pc parallel port, or can generate the ate or test vectors necessary for a third-party test system. ieee 1532-compliant in-system programming programming devices in-system provides a number of signi?ant bene?s including: rapid prototyping, lower inven- tory levels, higher quality and the ability to make in-?ld modi?ations. all ispmach 4000ze devices provide in- system programming (isp) capability through the boundary scan test access port. this capability has been implemented in a manner that ensures that the port remains complaint to the ieee 1149.1 standard. by using ieee 1149.1 as the communication interface through which isp is achieved, users get the bene? of a standard, well- de?ed interface. all ispmach 4000ze devices are also compliant with the ieee 1532 standard. the ispmach 4000ze devices can be programmed across the commercial temperature and voltage range. the pc-based lattice software facilitates in-system programming of ispmach 4000ze devices. the software takes the jedec ?e output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. the software can use these vectors to drive a scan chain via the parallel port of a pc. alternatively, the software can output ?es in formats understood by common auto- device macrocell block number mc number ispmach 4032ze osc mc timer mc a b 15 15 ispmach 4064ze osc mc timer mc a d 15 15 ispmach 4128ze osc mc timer mc a g 15 15 ispmach 4256ze osc mc timer mc c f 15 15
lattice semiconductor ispmach 4000ze family data sheet 17 mated test equipment. this equipment can then be used to program ispmach 4000ze devices during the testing of a circuit board. user electronic signature the user electronic signature (ues) allows the designer to include identi?ation bits or serial numbers inside the device, stored in e 2 cmos memory. the ispmach 4000ze device contains 32 ues bits that can be con?ured by the user to store unique data such as id codes, revision numbers or inventory control codes. security bit a programmable security bit is provided on the ispmach 4000ze devices as a deterrent to unauthorized copying of the array con?uration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and veri?ation are also defeated by the security bit. the bit can only be reset by erasing the entire device. hot socketing the ispmach 4000ze devices are well-suited for applications that require hot socketing capability. hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the i/os and inputs with- out being damaged. additionally, it requires that the effects of i/o pin loading be minimal on active signals. the ispmach 4000ze devices provide this capability for input voltages in the range 0v to 3.0v. density migration the ispmach 4000ze family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is possible to shift a lower utilization design tar- geted for a high density device to a lower density device. however, the exact details of the ?al resource utilization will impact the likely success in each case.
lattice semiconductor ispmach 4000ze family data sheet 18 absolute maximum ratings 1, 2, 3 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v output supply voltage (v cco ) . . . . . . . . . . . . . . . -0.5 to 4.5v input or i/o tristate voltage applied 4, 5 . . . . . . . . . -0.5 to 5.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150? junction temperature (t j ) with power applied . . . -55 to 150? 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. 2. compliance with lattice ther mal management document is required. 3. all voltages referenced to gnd. 4. undershoot of -2v and overshoot of (v ih (max) + 2v), up to a total pin voltage of 6v is permitted for a duration of <20ns. 5. maximum of 64 i/os per device with vin > 3.6v is allowed. recommended operating conditions erase reprogram speci?ations hot socketing characteristics 1,2,3 symbol parameter min. max. units v cc supply voltage standard voltage operation 1.7 1.9 v extended voltage operation 1.6 1 1.9 v t j junction temperature (commercial) 0 90 c junction temperature (industrial) -40 105 ? 1. devices operating at 1.6v can expect performance degradation up to 35%. parameter min. max. units erase/reprogram cycle 1,000 cycles note: valid over commercial temperature range. symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 v in 3.0v, tj = 105? ?0 ?50 ? 0 v in 3.0v, tj = 130? ?0 ?00 ? 1. insensitive to sequence of v cc or v cco. however, assumes monotonic rise/fall rates for v cc and v cco, provided (v in - v cco ) 3.6v. 2. 0 < v cc < v cc (max), 0 < v cco < v cco (max). 3. i dk is additive to i pu , i pd or i bh . device defaults to pull-up until fuse circuitry is active.
lattice semiconductor ispmach 4000ze family data sheet 19 i/o recommended operating conditions dc electrical characteristics over recommended operating conditions standard v cco (v) 1 min. max. lvttl 3.0 3.6 lvcmos 3.3 3.0 3.6 extended lvcmos 3.3 2.7 3.6 lvcmos 2.5 2.3 2.7 lvcmos 1.8 1.65 1.95 lvcmos 1.5 1.4 1.6 pci 3.3 3.0 3.6 1. typical values for v cco are the average of the min. and max. values. symbol parameter condition min. typ. max. units i il , i ih 1, 2 input leakage current 0 v in < v cco 0.5 1 a i ih 1 input high leakage current v cco < v in 5.5v 10 ? i pu i/o weak pull-up resistor current 0 v in 0.7v cco -20 -150 ? i pd i/o weak pull-down resistor current v il (max) v in v ih (min) 30 150 ? i bhls bus hold low sustaining current v in = v il (max) 30 ? i bhhs bus hold high sustaining current v in = 0.7 v cco -20 ? i bhlo bus hold low overdrive current 0v v in v bht 150 ? i bhho bus hold high overdrive current v bht v in v cco -150 ? v bht bus hold trip points v cco * 0.35 v cco * 0.65 v c 1 i/o capacitance 3 v cco = 3.3v, 2.5v, 1.8v, 1.5v 8 pf v cc = 1.8v, v io = 0 to v ih (max) c 2 clock capacitance 3 v cco = 3.3v, 2.5v, 1.8v, 1.5v 6 pf v cc = 1.8v, v io = 0 to v ih (max) c 3 global input capacitance 3 v cco = 3.3v, 2.5v, 1.8v, 1.5v 6 pf v cc = 1.8v, v io = 0 to v ih (max) 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tristated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. i ih excursions of up to 1.5? maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of the devices i/o pins. 3. measured t a = 25?, f = 1.0mhz.
lattice semiconductor ispmach 4000ze family data sheet 20 supply current symbol parameter condition min. typ. max. units ispmach 4032ze icc 1, 2, 3, 5, 6 operating power supply current vcc = 1.8v, t a = 25? 50 ? vcc = 1.9v, t a = 0 to 70? 58 ? vcc = 1.9v, t a = -40 to 85? 60 ? icc 4, 5, 6 standby power supply current vcc = 1.8v, t a = 25? 10 ? vcc = 1.9v, t a = 0 to 70? 13 25 a vcc = 1.9v, t a = -40 to 85? 15 40 a ispmach 4064ze icc 1, 2, 3, 5, 6 operating power supply current vcc = 1.8v, t a = 25? 80 ? vcc = 1.9v, t a = 0 to 70? 89 ? vcc = 1.9v, t a = -40 to 85? 92 ? icc 4, 5, 6 standby power supply current vcc = 1.8v, t a = 25? 11 ? vcc = 1.9v, t a = 0 to 70? 15 30 a vcc = 1.9v, t a = -40 to 85? 18 50 a ispmach 4128ze icc 1, 2, 3, 5, 6 operating power supply current vcc = 1.8v, t a = 25? 168 a vcc = 1.9v, t a = 0 to 70? 190 a vcc = 1.9v, t a = -40 to 85? 195 a icc 4, 5, 6 standby power supply current vcc = 1.8v, t a = 25? 12 ? vcc = 1.9v, t a = 0 to 70? 16 40 a vcc = 1.9v, t a = -40 to 85? 19 60 a ispmach 4256ze icc 1, 2, 3, 5, 6 operating power supply current vcc = 1.8v, t a = 25? 341 a vcc = 1.9v, t a = 0 to 70? 361 a vcc = 1.9v, t a = -40 to 85? 372 a icc 4, 5, 6 standby power supply current vcc = 1.8v, t a = 25? 13 ? vcc = 1.9v, t a = 0 to 70? 32 65 a vcc = 1.9v, t a = -40 to 85? 43 100 ? 1. frequency = 1.0 mhz. 2. device con?ured with 16-bit counters. 3. i cc varies with speci? device con?uration and operating frequency. 4. v cco = 3.6v, v in = 0v or v cco, bus maintenance turned off. v in above v cco will add transient current above the speci?d standby i cc . 5. includes v cco current without output loading. 6. this operating supply current is with the internal oscillator disabled. enabling the internal oscillator adds approximately 1 5? typical current plus additional current from any logic it drives.
lattice semiconductor ispmach 4000ze family data sheet 21 i/o dc electrical characteristics over recommended operating conditions standard v il v ih v ol max (v) v oh min (v) i ol 1 (ma) i oh 1 (ma) min (v) max (v) min (v) max (v) lvttl -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 3.3 -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 2.5 -0.3 0.70 1.70 3.6 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 1.8 -0.3 0.35 * v cc 0.65 * v cc 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 1.5 2 -0.3 0.35 * v cc 0.65 * v cc 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 pci 3.3 -0.3 0.3 * 3.3 * (v cc / 1.8) 0.5 * 3.3 * (v cc / 1.8) 5.5 0.1 v cco 0.9 v cco 1.5 -0.5 1. the average dc current drawn by i/os between adjacent bank gnd connections, or between the last gnd in an i/o bank and the e nd of the i/o bank, as shown in the logic signals connection table, shall not exceed n *8ma. where n is the number of i/os between bank gnd connections or between the last gnd in a bank and the end of a bank. 2. for 1.5v inputs, there may be an additional dc current drawn from v cc , if the ispmach 4000ze v cc and the v cc of the driving device (v cc d-d; that determines steady state v ih ) are in the extreme range of their speci?ations. typically, dc current drawn from v cc will be 2? per input. v o output voltage (v) 0 0 10 20 30 40 50 60 2.0 1.5 1.0 0.5 typical i/o output current (ma) 1.8v v cco i oh i ol
lattice semiconductor ispmach 4000ze family data sheet 22 ispmach 4000ze external switching characteristics over recommended operating conditions parameter description 1, 2 lc4032ze lc4064ze all devices units -4 -4 -5 -7 min. max. min. max. min. max. min. max. t pd 20-pt combinatorial propagation delay 4.4 4.7 5.8 7.5 ns t s glb register setup time before clock 2.2 2.5 2.9 4.5 ns t st glb register setup time before clock with t-type register 2.4 2.7 3.1 4.7 ns t sir glb register setup time before clock, input register path 1.0 1.1 1.3 1.4 ns t sirz glb register setup time before clock with zero hold 2.0 2.1 2.9 4.0 ns t h glb register hold time after clock 0.0 0.0 0.0 0.0 ns t ht glb register hold time after clock with t-type register 0.0 0.0 0.0 0.0 ns t hir glb register hold time after clock, input register path 1.0 1.0 1.3 1.3 ns t hirz glb register hold time after clock, input register path with zero hold 0.0 0.0 0.0 0.0 ns t co glb register clock-to-output delay 3.0 3.2 3.8 4.5 ns t r external reset pin to output delay 5.0 6.0 7.5 9.0 ns t rw external reset pulse duration 1.5 1.7 2.0 4.0 ns t ptoe/dis input to output local product term output enable/disable 7.0 8.0 8.2 9.0 ns t gptoe/dis input to output global product term output enable/disable 6.5 7.0 10.0 10.5 ns t goe/dis global oe input to output enable/disable 4.5 4.5 5.5 7.0 ns t cw global clock width, high or low 1.0 1.5 1.8 2.8 ns t gw global gate width low (for low transparent) or high (for high transparent) 1.0 1.5 1.8 2.8 ns t wir input register clock width, high or low 1.0 1.5 1.8 2.8 ns f max (int.) 3 clock frequency with internal feedback 260 241 200 172 mhz f max (ext.) clock frequency with external feedback, [1 / (t s + t co )] 192 175 149 111 mhz 1. timing numbers are based on default lvcmos 1.8 i/o buffers. use timing adjusters provided to calculate other standards. 2. measured using standard switching grp loading of 1 and 1 output switching. 3. standard 16-bit counter using grp feedback. timing v.0.8
lattice semiconductor ispmach 4000ze family data sheet 23 timing model the task of determining the timing through the ispmach 4000ze family, like any cpld, is relatively simple. the timing model provided in figure 16 shows the speci? delay paths. once the implementation of a given function is determined either conceptually or from the software report ?e, the delay path of the function can easily be deter- mined from the timing model. the lattice design tools report the timing delays based on the same timing model for a particular design. note that the internal timing parameters are given for reference only, and are not tested. the external timing parameters are tested and guaranteed for every device. for more information on the timing model and usage, refer to tn1168, ispma ch 4000ze timing model design and usage guidelines . figure 16. ispmach 4000ze timing model data mc reg. c.e. s/r q sclk in oe in/out delays oscillator/ timer delays in/out delays control delays register/latch delays routing/glb delays out note: italicized items are optional delay adders. t fbk feedback feedback from feedback t buf t mcell t ptclk t bclk t ptsr t bie t bsr t gptoe t ptoe t exp t route t oscdis t oscen t oscod t bla t inreg t indio t in t pgrt t ioi t gclk_in t ioi t pgrt t pgrt t goe t ioi t pdi t ioo t orp t en t dis
lattice semiconductor ispmach 4000ze family data sheet 24 ispmach 4000ze internal timing parameters over recommended operating conditions parameter description lc4032ze lc4064ze units -4 -4 min. max. min. max. in/out delays t in input buffer delay 0.85 0.90 ns t gclk_in global clock input buffer delay 1.60 1.60 ns t goe global oe pin delay 2.25 2.25 ns t buf delay through output buffer 0.75 0.90 ns t en output enable time 2.25 2.25 ns t dis output disable time 1.35 1.35 ns t pgsu input power guard setup time 3.30 3.55 ns t pgh input power guard hold time 0.00 0.00 ns t pgpw input power guard bie minimum pulse width 5.00 5.00 ns t pgrt input power guard recovery time following bie dissertation 5.00 5.00 ns routing delays t route delay through grp 1.60 1.70 ns t pdi macrocell propagation delay 0.25 0.25 ns t mcell macrocell delay 0.65 0.65 ns t inreg input buffer to macrocell register delay 0.90 1.00 ns t fbk internal feedback delay 0.55 0.55 ns t orp output routing pool delay 0.30 0.30 ns register/latch delays t s d-register setup time (global clock) 0.70 0.85 ns t s_pt d-register setup time (product term clock) 1.25 1.85 ns t h d-register hold time 1.50 1.65 ns t st t-register setup time (global clock) 0.90 1.05 ns t st_pt t-register setup time (product term clock) 1.45 1.65 ns t ht t-resister hold time 1.50 1.65 ns t sir d-input register setup time (global clock) 0.85 0.80 ns t sir_pt d-input register setup time (product term clock) 1.45 1.45 ns t hir d-input register hold time (global clock) 1.15 1.30 ns t hir_pt d-input register hold time (product term clock) 0.90 1.10 ns t coi register clock to output/feedback mux time 0.35 0.40 ns t ces clock enable setup time 1.00 2.00 ns t ceh clock enable hold time 0.00 0.00 ns t sl latch setup time (global clock) 0.70 0.95 ns t sl_pt latch setup time (product term clock) 1.45 1.85 ns t hl latch hold time 1.40 1.80 ns t goi latch gate to output/feedback mux time 0.40 0.35 ns t pdli propagation delay through transparent latch to output/ feedback mux 0.30 0.25 ns t sri asynchronous reset or set to output/feedback mux delay 0.30 0.30 ns
lattice semiconductor ispmach 4000ze family data sheet 25 t srr asynchronous reset or set recovery delay 2.00 1.70 ns control delays t bclk glb pt clock delay 1.20 1.30 ns t ptclk macrocell pt clock delay 1.40 1.50 ns t bsr block pt set/reset delay 1.10 1.85 ns t ptsr macrocell pt set/reset delay 1.20 1.90 ns t bie power guard block input enable delay 1.60 1.70 ns t ptoe macrocell pt oe delay 2.30 3.15 ns t gptoe global pt oe delay 1.80 2.15 ns internal oscillator t oscsu oscillator dynoscdis setup time 5.00 5.00 ns t osch oscillator dynoscdis hold time 5.00 5.00 ns t oscen oscillator oscout enable time (to stable) 5.00 5.00 ns t oscod oscillator output delay 4.00 4.00 ns t oscnom oscillator oscout nominal frequency 5.00 5.00 mhz t oscvar oscillator variation of nominal frequency 30 30 % t tmrco20 oscillator timerout clock (negative edge) to out (20-bit divider) 12.50 12.50 ns t tmrco10 oscillator timerout clock (negative edge) to out (10-bit divider) 7.50 7.50 ns t tmrco7 oscillator timerout clock (negative edge) to out (7-bit divider) 6.00 6.00 ns t tmrrsto oscillator timerout reset to out (going low) 5.00 5.00 ns t tmrrr oscillator timerout asynchronous reset recovery delay 4.00 4.00 ns t tmrrstpw oscillator timerout reset minimum pulse width 3.00 3.00 ns optional delay adjusters base parameter t indio input register delay t inreg 1.00 1.00 ns t exp product term expander delay t mcell 0.40 0.40 ns t bla additional block loading adders t route 0.04 0.05 ns t ioi input buffer delays lvttl_in using lvttl standard with hysteresis t in , t gclk_in , t goe 0.60 0.60 ns lvcmos15_in using lvcmos 1.5 standard t in , t gclk_in , t goe 0.20 0.20 ns lvcmos18_in using lvcmos 1.8 standard t in , t gclk_in , t goe 0.00 0.00 ns lvcmos25_in using lvcmos 2.5 standard with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns lvcmos33_in using lvcmos 3.3 standard with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns pci_in using pci compatible input with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns t ioo output buffer delays lvttl_out output con?ured as ttl buffer t en , t dis , t buf 0.20 0.20 ns ispmach 4000ze internal timing parameters (cont.) over recommended operating conditions parameter description lc4032ze lc4064ze units -4 -4 min. max. min. max.
lattice semiconductor ispmach 4000ze family data sheet 26 lvcmos15_out output con?ured as 1.5v buffer t en , t dis , t buf 0.20 0.20 ns lvcmos18_out output con?ured as 1.8v buffer t en , t dis , t buf 0.00 0.00 ns lvcmos25_out output con?ured as 2.5v buffer t en , t dis , t buf 0.10 0.10 ns lvcmos33_out output con?ured as 3.3v buffer t en , t dis , t buf 0.20 0.20 ns pci_out output con?ured as pci compati- ble buffer t en , t dis , t buf 0.20 0.20 ns slow slew output con?ured for slow slew rate t en , t buf 1.00 1.00 ns note: internal timing parameters are not tested and are for reference only. refer to the timing model in this data sheet for further details. timing v.0.8 ispmach 4000ze internal timing parameters (cont.) over recommended operating conditions parameter description lc4032ze lc4064ze units -4 -4 min. max. min. max.
lattice semiconductor ispmach 4000ze family data sheet 27 ispmach 4000ze internal timing parameters (cont.) over recommended operating conditions parameter description all devices units -5 -7 min. max. min. max. in/out delays t in input buffer delay 1.05 1.90 ns t gclk_in global clock input buffer delay 1.95 2.15 ns t goe global oe pin delay 3.00 4.30 ns t buf delay through output buffer 1.10 1.30 ns t en output enable time 2.50 2.70 ns t dis output disable time 2.50 2.70 ns t pgsu input power guard setup time 4.30 5.60 ns t pgh input power guard hold time 0.00 0.00 ns t pgpw input power guard bie minimum pulse width 6.00 8.00 ns t pgrt input power guard recovery time following bie dis- sertation 5.00 7.00 ns routing delays t route delay through grp 2.25 2.50 ns t pdi macrocell propagation delay 0.45 0.50 ns t mcell macrocell delay 0.65 1.00 ns t inreg input buffer to macrocell register delay 1.00 1.00 ns t fbk internal feedback delay 0.75 0.30 ns t orp output routing pool delay 0.30 0.30 ns register/latch delays t s d-register setup time (global clock) 0.90 1.25 ns t s_pt d-register setup time (product term clock) 2.00 2.35 ns t h d-register hold time 2.00 3.25 ns t st t-register setup time (global clock) 1.10 1.45 ns t st_pt t-register setup time (product term clock) 2.20 2.65 ns t ht t-resister hold time 2.00 3.25 ns t sir d-input register setup time (global clock) 1.20 0.65 ns t sir_pt d-input register setup time (product term clock) 1.45 1.45 ns t hir d-input register hold time (global clock) 1.40 2.05 ns t hir_pt d-input register hold time (product term clock) 1.10 1.20 ns t coi register clock to output/feedback mux time 0.45 0.75 ns t ces clock enable setup time 2.00 2.00 ns t ceh clock enable hold time 0.00 0.00 ns t sl latch setup time (global clock) 0.90 1.55 ns t sl_pt latch setup time (product term clock) 2.00 2.05 ns t hl latch hold time 2.00 1.17 ns t goi latch gate to output/feedback mux time 0.35 0.33 ns t pdli propagation delay through transparent latch to output/ feedback mux 0.25 0.25 ns t sri asynchronous reset or set to output/feedback mux delay 0.95 0.28 ns
lattice semiconductor ispmach 4000ze family data sheet 28 t srr asynchronous reset or set recovery delay 1.80 1.67 ns control delays t bclk glb pt clock delay 1.45 0.95 ns t ptclk macrocell pt clock delay 1.45 1.15 ns t bsr block pt set/reset delay 1.85 1.83 ns t ptsr macrocell pt set/reset delay 1.85 2.72 ns t bie power guard block input enable delay 1.75 1.95 ns t ptoe macrocell pt oe delay 2.40 1.90 ns t gptoe global pt oe delay 4.20 3.40 ns internal oscillator t oscsu oscillator dynoscdis setup time 5.00 5.00 ns t osch oscillator dynoscdis hold time 5.00 5.00 ns t oscen oscillator oscout enable time (to stable) 5.00 5.00 ns t oscod oscillator output delay 4.00 4.00 ns t oscnom oscillator oscout nominal frequency 5.00 5.00 mhz t oscvar oscillator variation of nominal frequency 30 30 % t tmrco20 oscillator timerout clock (negative edge) to out (20-bit divider) 12.50 14.50 ns t tmrco10 oscillator timerout clock (negative edge) to out (10-bit divider) 7.50 9.50 ns t tmrco7 oscillator timerout clock (negative edge) to out (7-bit divider) 6.00 8.00 ns t tmrrsto oscillator timerout reset to out (going low) 5.00 7.00 ns t tmrrr oscillator timerout asynchronous reset recovery delay 4.00 6.00 ns t tmrrstpw oscillator timerout reset minimum pulse width 3.00 5.00 ns optional delay adjusters base parameter t indio input register delay t inreg 1.60 2.60 ns t exp product term expander delay t mcell 0.45 0.50 ns t bla additional block loading adders t route 0.05 0.05 ns t ioi input buffer delays lvttl_in using lvttl standard with hysteresis t in , t gclk_in , t goe 0.60 0.60 ns lvcmos15_in using lvcmos 1.5 standard t in , t gclk_in , t goe 0.20 0.20 ns lvcmos18_in using lvcmos 1.8 standard t in , t gclk_in , t goe 0.00 0.00 ns lvcmos25_in using lvcmos 2.5 standard with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns lvcmos33_in using lvcmos 3.3 standard with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns pci_in using pci compatible input with hysteresis t in , t gclk_in , t goe 0.80 0.80 ns t ioo output buffer delays lvttl_out output con?ured as ttl buffer t en , t dis , t buf 0.20 0.20 ns ispmach 4000ze internal timing parameters (cont.) over recommended operating conditions parameter description all devices units -5 -7 min. max. min. max.
lattice semiconductor ispmach 4000ze family data sheet 29 lvcmos15_out output con?ured as 1.5v buffer t en , t dis , t buf 0.20 0.20 ns lvcmos18_out output con?ured as 1.8v buffer t en , t dis , t buf 0.00 0.00 ns lvcmos25_out output con?ured as 2.5v buffer t en , t dis , t buf 0.10 0.10 ns lvcmos33_out output con?ured as 3.3v buffer t en , t dis , t buf 0.20 0.20 ns pci_out output con?ured as pci compati- ble buffer t en , t dis , t buf 0.20 0.20 ns slow slew output con?ured for slow slew rate t en , t buf 1.00 1.00 ns note: internal timing parameters are not tested and are for reference only. refer to the timing model in this data sheet for further details. timing v.0.8 ispmach 4000ze internal timing parameters (cont.) over recommended operating conditions parameter description all devices units -5 -7 min. max. min. max.
lattice semiconductor ispmach 4000ze family data sheet 30 boundary scan waveforms and timing speci?ations symbol parameter min. max. units t btcp tck [bscan test] clock cycle 40 ns t btch tck [bscan test] pulse width high 20 ns t btcl tck [bscan test] pulse width low 20 ns t btsu tck [bscan test] setup time 8 ns t bth tck [bscan test] hold time 10 ns t brf tck [bscan test] rise and fall time 50 mv/ns t btco tap controller falling edge of clock to valid output 10 ns t btoz tap controller falling edge of clock to data output disable 10 ns t btvo tap controller falling edge of clock to data output enable 10 ns t btcpsu bscan test capture register setup time 8 ns t btcph bscan test capture register hold time 10 ns t btuco bscan test update reg, falling edge of clock to valid output 25 ns t btuoz bscan test update reg, falling edge of clock to output disable 25 ns t btuov bscan test update reg, falling edge of clock to output enable 25 ns
lattice semiconductor ispmach 4000ze family data sheet 31 power consumption power estimation coef?ients 1 device a b ispmach 4032ze 0.010 0.009 ispmach 4064ze 0.011 0.009 ispmach 4128ze 0.012 0.009 ispmach 4256ze 0.013 0.009 1. for further information about the use of these coef?ients, refer to tn1187, p o w er esti- mation in ispma ch 4000ze de vices . 4032ze 4064ze 4128ze 4256ze ispmach 4000ze typical i cc vs. frequency 0 0 50 100 150 200 250 300 10 20 30 40 50 60 70 frequency (mhz) icc (ma)
lattice semiconductor ispmach 4000ze family data sheet 32 switching test conditions figure 17 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, voltage, and other test conditions are shown in table 13. figure 17. output test load, lvttl and lvcmos standards table 13. test fixture required components test condition r 1 r 2 c l 1 timing ref. v cco lvcmos i/o, (l -> h, h -> l) 106 106 35pf lvcmos 3.3 = 1.5v lvcmos 3.3 = 3.0v lvcmos 2.5 = 2.3v lvcmos 1.8 = 1.65v lvcmos 1.5 = 1.4v lvcmos i/o (z -> h) 106 35pf 1.5v 3.0v lvcmos i/o (z -> l) 106 ? 35pf 1.5v 3.0v lvcmos i/o (h -> z) 106 5pf v oh - 0.3 3.0v lvcmos i/o (l -> z) 106 ? 5pf v ol + 0.3 3.0v 1. c l includes test ?tures and probe capacitance. v cco r 1 r 2 c l dut test point 0213a/ispm4k l v cmos 2.5 = v cco 2 l v cmos 1. 8 = v cco 2 l v cmos 1.5 = v cco 2
lattice semiconductor ispmach 4000ze family data sheet 33 signal descriptions orp reference table signal names description tms input ?this pin is the ieee 1149.1 test mode select input, which is used to control the state machine. tck input ?this pin is the ieee 1149.1 test clock input pin, used to clock through the state machine. tdi input ?this pin is the ieee 1149.1 test data in pin, used to load data. tdo output ?this pin is the ieee 1149.1 test data out pin used to shift data out. goe0/io, goe1/io these pins are con?ured to be either global output enable input or as general i/o pins. gnd ground nc not connected v cc the power supply pins for logic core and jtag port. clk0/i, clk1/i, clk2/i, clk3/i these pins are con?ured to be either clk input or as an input. v cco0 , v cco1 the power supply pins for each i/o bank. yzz input/output 1 ?these are the general purpose i/o used by the logic array. y is glb reference (alpha) and z is macrocell reference (numeric). z: 0-15. ispmach 4032ze y: a-b ispmach 4064ze y: a-d ispmach 4128ze y: a-h ispmach 4256ze y: a-p 1. in some packages, certain i/os are only available for use as inputs. see the logic signal connections tables for details. 4032ze 4064ze 4128ze 4256ze number of i/os 32 32 48 64 64 96 64 96 108 number of glbs 244488161616 number of i/os per glb 16 8 mixture of 9, 10, 14, 15 16 8 12 4 6 mixture of 6, 7, 8 reference orp table (i/os per glb) 16 8 9, 10, 14, 15 16 8 12 4 6 6, 7, 8
lattice semiconductor ispmach 4000ze family data sheet 34 ispmach 4000ze power supply and nc connections 1 signal 48 tqfp 2 64 csbga 3, 4 64 ucbga 3, 4 100 tqfp 2 vcc 12, 36 e4, d5 e4, d5 25, 40, 75, 90 vcco0 vcco (bank 0) 6 4032ze: e3 4064ze: e3, f4 c3, f3 13, 33, 95 vcco1 vcco (bank 1) 30 4032ze: d6 4064ze: d6, c6 f6, a6 45, 63, 83 gnd 13, 37 d4, e5 d4, d5 1, 26, 51, 76 gnd (bank 0) 5 d4, e5 d4, d5 7, 18, 32, 96 gnd (bank 1) 29 d4, e5 d4, d5 46, 57, 68, 82 nc 1. all grounds must be electrically connected at the board level. however, for the purposes of i/o current loading, grounds are associated with the bank shown. 2. pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4. all bonded grounds are connected to the following two balls, d4 and e5.
lattice semiconductor ispmach 4000ze family data sheet 35 ispmach 4000ze power supply and nc connections 1 (cont.) signal 132 ucbga 3 144 csbga 3 144 tqfp 2 vcc m1, m7, a12, b5 h5, h8, e8, e5 36, 57, 108, 129 vcco0 vcco (bank 0) b1, h4, l2, j5, a4 e4, f4, g4, j5, d5 3, 19, 34, 47, 136 vcco1 vcco (bank 1) k9, l12, f12, d9, c7 j8, h9, g9, f9, d8 64, 75, 91, 106, 119 gnd e5, e8, h5, h8 f6, g6, g7, f7 1, 37, 73, 109 gnd (bank 0) e2, h2, m4, b7, b3 g5, h4, h6, e6, f5 10, 18 4 , 27, 46, 127, 137 gnd (bank 1) l7, j9, h12, e9, a9 h7, j9, g8, f8, e7 55, 65, 82, 90 4 , 99, 118 nc 4064ze: e4, b2, b1, d2, d3, e1, h1, h3, h2, l1, g4, m1, k3, m2, m4, l5, h7, l8, m8, l10, k9, m11, h9, l12, l11, j12, j11, h10, d10, f10, d12, b12, f9, a12, c10, b10, a9, b8, e6, b5, a5, c4, b3, a2 4128ze: d2, d3, h2, m1, k3, m11, j12, j11, d12, a12, c10, a2 4128ze: 17, 20, 38, 45, 72, 89, 92, 110, 117, 144 4256ze: 18, 90 1. all grounds must be electrically connected at the board level. however, for the purposes of i/o current loading, grounds are associated with the bank shown. 2. pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4. for the lc4256ze, pins 18 and 90 are no connects.
lattice semiconductor ispmach 4000ze family data sheet 36 ispmach 4032ze and 4064ze logic signal connections: 48 tqfp pin number bank number ispmach 4032ze ispmach 4064ze glb/mc/pad glb/mc/pad 1 - tdi tdi 2 0 a5 a8 3 0 a6 a10 4 0 a7 a11 5 0 gnd (bank 0) gnd (bank 0) 6 0 vcco (bank 0) vcco (bank 0) 7 0 a8 b15 8 0 a9 b12 9 0 a10 b10 10 0 a11 b8 11 - tck tck 12 - vcc vcc 13 - gnd gnd 14 0 a12 b6 15 0 a13 b4 16 0 a14 b2 17 0 a15 b0 18 0 clk1/i clk1/i 19 1 clk2/i clk2/i 20 1 b0 c0 21 1 b1 c1 22 1 b2 c2 23 1 b3 c4 24 1 b4 c6 25 - tms tms 26 1 b5 c8 27 1 b6 c10 28 1 b7 c11 29 1 gnd (bank 1) gnd (bank 1) 30 1 vcco (bank 1) vcco (bank 1) 31 1 b8 d15 32 1 b9 d12 33 1 b10 d10 34 1 b11 d8 35 - tdo tdo 36 - vcc vcc 37 - gnd gnd 38 1 b12 d6 39 1 b13 d4 40 1 b14 d2 41 1 b15/goe1 d0/goe1 42 1 clk3/i clk3/i
lattice semiconductor ispmach 4000ze family data sheet 37 43 0 clk0/i clk0/i 44 0 a0/goe0 a0/goe0 45 0 a1 a1 46 0 a2 a2 47 0 a3 a4 48 0 a4 a6 ispmach 4032ze and 4064ze logic signal connections: 48 tqfp (cont.) pin number bank number ispmach 4032ze ispmach 4064ze glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 38 ispmach 4032ze and 4064ze logic signal connections: 64 csbga ball number bank number ispmach 4032ze ispmach 4064ze glb/mc/pad glb/mc/pad b2 - tdi tdi b10a5a8 c2 0 a6 a10 c1 0 a7 a11 gnd* 0 gnd (bank 0) gnd (bank 0) c3 0 nc a12 e3 0 vcco (bank 0) vcco (bank 0) d1 0 a8 b15 d2 0 nc b14 e1 0 a9 b13 d3 0 a10 b12 f1 0 a11 b11 e2 0 nc b10 g1 0 nc b9 f2 0 nc b8 h1 - tck tck e4 - vcc vcc gnd* - gnd gnd g2 0 a12 b6 h2 0 nc b5 h3 0 a13 b4 gnd* 0 nc gnd (bank 0) f4 0 nc vcco (bank 0) g3 0 a14 b3 f3 0 nc b2 h4 0 a15 b0 g4 0 clk1/i clk1/i h5 1 clk2/i clk2/i f5 1 b0 c0 g5 1 b1 c1 g6 1 b2 c2 h6 1 b3 c4 f6 1 b4 c5 h7 1 nc c6 h8 - tms tms g7 1 b5 c8 f7 1 b6 c10 g8 1 b7 c11 gnd* 1 gnd (bank 0) gnd (bank 1) f8 1 nc c12 d6 1 vcco (bank 1) vcco (bank 1) e8 1 b8 d15
lattice semiconductor ispmach 4000ze family data sheet 39 e7 1 nc d14 e6 1 b9 d13 d7 1 b10 d12 d8 1 nc d11 c5 1 nc d10 c7 1 b11 d9 c8 1 nc d8 b8 - tdo tdo d5 - vcc vcc gnd* - gnd gnd a8 1 b12 d7 a7 1 nc d6 b7 1 nc d5 a6 1 b13 d4 gnd* 1 nc gnd (bank 1) c6 1 nc vcco (bank 1) b6 1 b14 d3 a5 1 nc d2 b5 1 b15/goe1 d0/goe1 a4 1 clk3/i clk3/i c4 0 clk0/i clk0/i b4 0 a0/goe0 a0/goe0 b30a1a1 a30a2a2 a20a3a4 a10a4a6 * all bonded grounds are connected to the following two balls, d4 and e5. ispmach 4032ze and 4064ze logic signal connections: 64 csbga (cont.) ball number bank number ispmach 4032ze ispmach 4064ze glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 40 ispmach 4064ze logic signal connections: 64 ucbga ball number bank number glb/mc/pad a1 - tdi b10a8 b2 0 a10 b3 0 a11 gnd* 0 gnd (bank 0) c1 0 a12 c3 0 vcco (bank 0) c2 0 b15 d1 0 b14 d2 0 b13 d3 0 b12 e1 0 b11 e2 0 b10 e30b9 f1 0 b8 f2 - tck e4 - vcc gnd* - gnd h2 0 b6 h1 0 b5 g1 0 b4 gnd* 0 gnd (bank 0) f3 0 vcco (bank 0) g2 0 b3 g3 0 b2 h3 0 b0 g4 0 clk1/i f4 1 clk2/i h41c0 h51c1 g5 1 c2 h61c4 h71c5 h81c6 g8 - tms g7 1 c8 g6 1 c10 f8 1 c11 gnd* 1 gnd (bank 1) f7 1 c12 f6 1 vcco (bank 1) f5 1 d15 e8 1 d14
lattice semiconductor ispmach 4000ze family data sheet 41 e7 1 d13 e6 1 d12 d8 1 d11 d7 1 d10 d61d9 c81d8 c7 - tdo d5 - vcc gnd* - gnd b8 1 d7 a8 1 d6 b7 1 d5 a7 1 d4 gnd* 1 gnd (bank 1) a6 1 vcco (bank 1) b6 1 d3 c61d2 a5 1 d0/goe1 b5 1 clk3/i c5 0 clk0/i a4 0 a0/goe0 b40a1 c4 0 a2 a30a4 a20a6 * all bonded grounds are connected to the following two balls, d4 and e5. ispmach 4064ze logic signal connections: 64 ucbga (cont.) ball number bank number glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 42 ispmach 4064ze, 4128ze and 4256ze logic signal connections: 100 tqfp pin number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad 1 - gnd gnd gnd 2 - tdi tdi tdi 3 0 a8 b0 c12 4 0 a9 b2 c10 5 0 a10 b4 c6 6 0 a11 b6 c2 7 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) 8 0 a12 b8 d12 9 0 a13 b10 d10 10 0 a14 b12 d6 11 0 a15 b13 d4 12* 0 i i i 13 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) 14 0 b15 c14 e4 15 0 b14 c12 e6 16 0 b13 c10 e10 17 0 b12 c8 e12 18 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) 19 0 b11 c6 f2 20 0 b10 c5 f6 21 0 b9 c4 f10 22 0 b8 c2 f12 23* 0 i i i 24 - tck tck tck 25 - vcc vcc vcc 26 - gnd gnd gnd 27* 0 i i i 28 0 b7 d13 g12 29 0 b6 d12 g10 30 0 b5 d10 g6 31 0 b4 d8 g2 32 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) 33 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) 34 0 b3 d6 h12 35 0 b2 d4 h10 36 0 b1 d2 h6 37 0 b0 d0 h2 38 0 clk1/i clk1/i clk1/i 39 1 clk2/i clk2/i clk2/i 40 - vcc vcc vcc 41 1 c0 e0 i2
lattice semiconductor ispmach 4000ze family data sheet 43 42 1 c1 e2 i6 43 1 c2 e4 i10 44 1 c3 e6 i12 45 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) 46 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) 47 1 c4 e8 j2 48 1 c5 e10 j6 49 1 c6 e12 j10 50 1 c7 e14 j12 51 - gnd gnd gnd 52 - tms tms tms 53 1 c8 f0 k12 54 1 c9 f2 k10 55 1 c10 f4 k6 56 1 c11 f6 k2 57 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) 58 1 c12 f8 l12 59 1 c13 f10 l10 60 1 c14 f12 l6 61 1 c15 f13 l4 62* 1 i i i 63 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) 64 1 d15 g14 m4 65 1 d14 g12 m6 66 1 d13 g10 m10 67 1 d12 g8 m12 68 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) 69 1 d11 g6 n2 70 1 d10 g5 n6 71 1 d9 g4 n10 72 1 d8 g2 n12 73* 1 i i i 74 - tdo tdo tdo 75 - vcc vcc vcc 76 - gnd gnd gnd 77* 1 i i i 78 1 d7 h13 o12 79 1 d6 h12 o10 80 1 d5 h10 o6 81 1 d4 h8 o2 82 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) ispmach 4064ze, 4128ze and 4256ze logic signal connections: 100 tqfp (cont.) pin number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 44 83 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) 84 1 d3 h6 p12 85 1 d2 h4 p10 86 1 d1 h2 p6 87 1 d0/goe1 h0/goe1 p2/goe1 88 1 clk3/i clk3/i clk3/i 89 0 clk0/i clk0/i clk0/i 90 - vcc vcc vcc 91 0 a0/goe0 a0/goe0 a2/goe0 920a1a2a6 93 0 a2 a4 a10 94 0 a3 a6 a12 95 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) 96 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) 970a4a8b2 98 0 a5 a10 b6 99 0 a6 a12 b10 100 0 a7 a14 b12 * this pin is input only. ispmach 4064ze, 4128ze and 4256ze logic signal connections: 100 tqfp (cont.) pin number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 45 ispmach 4128ze logic signal connections: 132 ucbga ball number bank number glb/mc/pad gnd* - gnd a1 - tdi b1 0 vcco (bank 0) d3 0 b0 c1 0 b1 d2 0 b2 d1 0 b4 e40b5 f3 0 b6 e2 0 gnd (bank 0) e10b8 e30b9 f4 0 b10 g4 0 b12 f2 0 b13 g3 0 b14 h4 0 vcco (bank 0) f1 0 c14 g2 0 c13 g1 0 c12 h3 0 c10 j4 0 c9 h10c8 h2 0 gnd (bank 0) j3 0 c6 j1 0 c5 j2 0 c4 k3 0 c2 k2 0 c1 k1 0 c0 l2 0 vcco (bank 0) l1 - tck m1 - vcc gnd* - gnd l3 0 d14 m2 0 d13 k4 0 d12 m3 0 d10 k5 0 d9 l4 0 d8 m4 0 gnd (bank 0) j5 0 vcco (bank 0) l5 0 d6
lattice semiconductor ispmach 4000ze family data sheet 46 m5 0 d5 j6 0 d4 k6 0 d2 l6 0 d1 m6 0 d0 k7 0 clk1/i l7 1 gnd (bank 1) j7 1 clk2/i m7 - vcc k81e0 l8 1 e1 m8 1 e2 j8 1 e4 l9 1 e5 m9 1 e6 k9 1 vcco (bank 1) j9 1 gnd (bank 1) l10 1 e8 k10 1 e9 m10 1 e10 l11 1 e12 k12 1 e13 m11 1 e14 gnd* - gnd m12 - tms l12 1 vcco (bank 1) k11 1 f0 j10 1 f1 h9 1 f2 j12 1 f4 j11 1 f5 h10 1 f6 h12 1 gnd (bank 1) g9 1 f8 h11 1 f9 f9 1 f10 g12 1 f12 g11 1 f13 g10 1 f14 f12 1 vcco (bank 1) f10 1 g14 f11 1 g13 e11 1 g12 e10 1 g10 ispmach 4128ze logic signal connections: 132 ucbga (cont.) ball number bank number glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 47 d10 1 g9 e12 1 g8 e9 1 gnd (bank 1) d12 1 g6 d11 1 g5 c12 1 g4 c10 1 g2 c11 1 g1 b11 1 g0 d9 1 vcco (bank 1) b12 - tdo a12 - vcc gnd* - gnd a10 1 h14 a11 1 h13 b10 1 h12 c9 1 h10 d81h9 c81h8 a9 1 gnd (bank 1) c7 1 vcco (bank 1) b9 1 h6 b8 1 h5 d71h4 a8 1 h2 a7 1 h1 b6 1 h0/goe1 c6 1 clk3/i b7 0 gnd (bank 0) d6 0 clk0/i b5 - vcc a6 0 a0/goe0 c5 0 a1 b40a2 a50a4 c4 0 a5 d5 0 a6 a4 0 vcco (bank 0) b3 0 gnd (bank 0) d4 0 a8 a30a9 c3 0 a10 b2 0 a12 c2 0 a13 ispmach 4128ze logic signal connections: 132 ucbga (cont.) ball number bank number glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 48 a2 0 a14 * all bonded core grounds are connected to the following four balls, e5, e8, h5 and h8. ispmach 4128ze logic signal connections: 132 ucbga (cont.) ball number bank number glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 49 ispmach 4064ze, 4128ze and 4256ze logic signal connections: 144 csbga ball number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad f6 - gnd gnd gnd a1 - tdi tdi tdi e4 0 nc ball vcco (bank 0) vcco (bank 0) b2 0 nc ball b0 c12 b1 0 nc ball b1 c10 c3 0 a8 b2 c8 c2 0 a9 b4 c6 c1 0 a10 b5 c4 d1 0 a11 b6 c2 g5 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) d2 0 nc ball nc ball d14 d3 0 nc ball nc ball d12 e1 0 nc ball b8 d10 e2 0 a12 b9 d8 f2 0 a13 b10 d6 d4 0 a14 b12 d4 f1 0 a15 b13 d2 f3* 0 i b14 d0 f4 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) g1 0 b15 c14 e0 e3 0 b14 c13 e2 g2 0 b13 c12 e4 g3 0 b12 c10 e6 h1 0 nc ball c9 e8 h3 0 nc ball c8 e10 h2 0 nc ball nc ball e12 h4 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) j1 0 b11 c6 f2 j3 0 b10 c5 f4 j2 0 b9 c4 f6 k1 0 b8 c2 f8 k2* 0 i c1 f10 l1 0 nc ball c0 f12 g4 0 nc ball vcco (bank 0) vcco (bank 0) l2 - tck tck tck h5 - vcc vcc vcc g6 - gnd gnd gnd m1 0 nc ball nc ball g14 k3 0 nc ball nc ball g12 m2 0 nc ball d14 g10 l3* 0 i d13 g8
lattice semiconductor ispmach 4000ze family data sheet 50 j4 0 b7 d12 g6 k4 0 b6 d10 g4 m3 0 b5 d9 g2 l4 0 b4 d8 g0 h6 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) j5 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) m4 0 nc ball d6 h12 l5 0 nc ball d5 h10 k5 0 b3 d4 h8 j6 0 b2 d2 h6 m5 0 b1 d1 h4 k6 0 b0 d0 h2 l6 0 clk1/i clk1/i clk1/i h7 1 nc ball gnd (bank 1) gnd (bank 1) m6 1 clk2/i clk2/i clk2/i h8 - vcc vcc vcc k7 1 c0 e0 i2 m7 1 c1 e1 i4 l7 1 c2 e2 i6 j7 1 c3 e4 i8 l8 1 nc ball e5 i10 m8 1 nc ball e6 i12 j8 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) j9 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) m9 1 c4 e8 j2 l9 1 c5 e9 j4 k8 1 c6 e10 j6 m10 1 c7 e12 j8 l10 1 nc ball e13 j10 k9 1 nc ball e14 j12 m11 1 nc ball nc ball j14 g7 - gnd gnd gnd m12 - tms tms tms h9 1 nc ball vcco (bank 1) vcco (bank 1) l12 1 nc ball f0 k12 l11 1 nc ball f1 k10 k10 1 c8 f2 k8 k12 1 c9 f4 k6 j10 1 c10 f5 k4 k11 1 c11 f6 k2 g8 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) ispmach 4064ze, 4128ze and 4256ze logic signal connections: 144 csbga (cont.) ball number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 51 j12 1 nc ball nc ball l14 j11 1 nc ball nc ball l12 h10 1 nc ball f8 l10 h12 1 c12 f9 l8 g11 1 c13 f10 l6 h11 1 c14 f12 l4 g12 1 c15 f13 l2 g10* 1 i f14 l0 g9 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) f12 1 d15 g14 m0 f11 1 d14 g13 m2 e11 1 d13 g12 m4 e12 1 d12 g10 m6 d10 1 nc ball g9 m8 f10 1 nc ball g8 m10 d12 1 nc ball nc ball m12 f8 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) e10 1 d11 g6 n2 d11 1 d10 g5 n4 e91d9g4n6 c121d8g2n8 c11* 1 i g1 n10 b12 1 nc ball g0 n12 f9 1 nc ball vcco (bank 1) vcco (bank 1) b11 - tdo tdo tdo e8 - vcc vcc vcc f7 - gnd gnd gnd a12 1 nc ball nc ball o14 c10 1 nc ball nc ball o12 b10 1 nc ball h14 o10 a11* 1 i h13 o8 d9 1 d7 h12 o6 b9 1 d6 h10 o4 c9 1 d5 h9 o2 a10 1 d4 h8 o0 e7 1 gnd (bank 1) gnd (bank 1) gnd (bank 1) d8 1 vcco (bank 1) vcco (bank 1) vcco (bank 1) a9 1 nc ball h6 p12 b8 1 nc ball h5 p10 c8 1 d3 h4 p8 a8 1 d2 h2 p6 d7 1 d1 h1 p4 b7 1 d0/goe1 h0/goe1 p2/goe1 ispmach 4064ze, 4128ze and 4256ze logic signal connections: 144 csbga (cont.) ball number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 52 c7 1 clk3/i clk3/i clk3/i e6 0 nc ball gnd (bank 0) gnd (bank 0) a7 0 clk0/i clk0/i clk0/i e5 - vcc vcc vcc d6 0 a0/goe0 a0/goe0 a2/goe0 b60a1a1a4 a60a2a2a6 c60a3a4a8 b5 0 nc ball a5 a10 a5 0 nc ball a6 a12 d5 0 vcco (bank 0) vcco (bank 0) vcco (bank 0) f5 0 gnd (bank 0) gnd (bank 0) gnd (bank 0) a40a4a8b2 b40a5a9b4 c5 0 a6 a10 b6 a3 0 a7 a12 b8 c4 0 nc ball a13 b10 b3 0 nc ball a14 b12 a2 0 nc ball nc ball b14 * this pin is input only for the lc4064ze. ispmach 4064ze, 4128ze and 4256ze logic signal connections: 144 csbga (cont.) ball number bank number lc4064ze lc4128ze lc4256ze glb/mc/pad glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 53 ispmach 4128ze and 4256ze logic signal connections: 144 tqfp pin number bank number lc4128ze lc4256ze glb/mc/pad glb/mc/pad 1 - gnd gnd 2 - tdi tdi 3 0 vcco (bank 0) vcco (bank 0) 4 0 b0 c12 5 0 b1 c10 6 0 b2 c8 7 0 b4 c6 8 0 b5 c4 9 0 b6 c2 10 0 gnd (bank 0) gnd (bank 0) 11 0 b8 d14 12 0 b9 d12 13 0 b10 d10 14 0 b12 d8 15 0 b13 d6 16 0 b14 d4 17* 0 nc i 18 0 gnd (bank 0) nc 19 0 vcco (bank 0) vcco (bank 0) 20* 0 nc i 21 0 c14 e2 22 0 c13 e4 23 0 c12 e6 24 0 c10 e8 25 0 c9 e10 26 0 c8 e12 27 0 gnd (bank 0) gnd (bank 0) 28 0 c6 f2 29 0 c5 f4 30 0 c4 f6 31 0 c2 f8 32 0 c1 f10 33 0 c0 f12 34 0 vcco (bank 0) vcco (bank 0) 35 - tck tck 36 - vcc vcc 37 - gnd gnd 38* 0 nc i 39 0 d14 g12 40 0 d13 g10 41 0 d12 g8 42 0 d10 g6
lattice semiconductor ispmach 4000ze family data sheet 54 43 0 d9 g4 44 0 d8 g2 45* 0 nc i 46 0 gnd (bank 0) gnd (bank 0) 47 0 vcco (bank 0) vcco (bank 0) 48 0 d6 h12 49 0 d5 h10 50 0 d4 h8 51 0 d2 h6 52 0 d1 h4 53 0 d0 h2 54 0 clk1/i clk1/i 55 1 gnd (bank 1) gnd (bank 1) 56 1 clk2/i clk2/i 57 - vcc vcc 58 1 e0 i2 59 1 e1 i4 60 1 e2 i6 61 1 e4 i8 62 1 e5 i10 63 1 e6 i12 64 1 vcco (bank 1) vcco (bank 1) 65 1 gnd (bank 1) gnd (bank 1) 66 1 e8 j2 67 1 e9 j4 68 1 e10 j6 69 1 e12 j8 70 1 e13 j10 71 1 e14 j12 72* 1 nc i 73 - gnd gnd 74 - tms tms 75 1 vcco (bank 1) vcco (bank 1) 76 1 f0 k12 77 1 f1 k10 78 1 f2 k8 79 1 f4 k6 80 1 f5 k4 81 1 f6 k2 82 1 gnd (bank 1) gnd (bank 1) 83 1 f8 l14 84 1 f9 l12 85 1 f10 l10 ispmach 4128ze and 4256ze logic signal connections: 144 tqfp (cont.) pin number bank number lc4128ze lc4256ze glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 55 86 1 f12 l8 87 1 f13 l6 88 1 f14 l4 89* 1 nc i 90 1 gnd (bank 1) nc 91 1 vcco (bank 1) vcco (bank 1) 92* 1 nc i 93 1 g14 m2 94 1 g13 m4 95 1 g12 m6 96 1 g10 m8 97 1 g9 m10 98 1 g8 m12 99 1 gnd (bank 1) gnd (bank 1) 100 1 g6 n2 101 1 g5 n4 102 1 g4 n6 103 1 g2 n8 104 1 g1 n10 105 1 g0 n12 106 1 vcco (bank 1) vcco (bank 1) 107 - tdo tdo 108 - vcc vcc 109 - gnd gnd 110* 1 nc i 111 1 h14 o12 112 1 h13 o10 113 1 h12 o8 114 1 h10 o6 115 1 h9 o4 116 1 h8 o2 117* 1 nc i 118 1 gnd (bank 1) gnd (bank 1) 119 1 vcco (bank 1) vcco (bank 1) 120 1 h6 p12 121 1 h5 p10 122 1 h4 p8 123 1 h2 p6 124 1 h1 p4 125 1 h0/goe1 p2/goe1 126 1 clk3/i clk3/i 127 0 gnd (bank 0) gnd (bank 0) 128 0 clk0/i clk0/i ispmach 4128ze and 4256ze logic signal connections: 144 tqfp (cont.) pin number bank number lc4128ze lc4256ze glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 56 129 - vcc vcc 130 0 a0/goe0 a2/goe0 131 0 a1 a4 132 0 a2 a6 133 0 a4 a8 134 0 a5 a10 135 0 a6 a12 136 0 vcco (bank 0) vcco (bank 0) 137 0 gnd (bank 0) gnd (bank 0) 138 0 a8 b2 139 0 a9 b4 140 0 a10 b6 141 0 a12 b8 142 0 a13 b10 143 0 a14 b12 144* 0 nc i * this pin is input only for the lc4256ze. ispmach 4128ze and 4256ze logic signal connections: 144 tqfp (cont.) pin number bank number lc4128ze lc4256ze glb/mc/pad glb/mc/pad
lattice semiconductor ispmach 4000ze family data sheet 57 part number description ispmach 4000ze family speed grade offering ordering information note: ispmach 4000ze devices are dual marked except for the slowest commercial speed grade. for example, the commercial speed grade lc4128ze-5tn100c is also marked with the industrial grade -7i. the commercial grade is always one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade devices are marked as commercial grade only. the markings appear as follows: figure 18. mark format for 100 tqfp and 144 tqfp packages figure 19. mark format for 48 tqfp, 64 csbga and 144 csbga packages -4 -5 -7 com com ind com ind ispmach 4032ze ? ?? ? ? ispmach 4064ze ? ?? ? ? ispmach 4128ze ? ? ? ispmach 4256ze ? ? ? device number 4032 = 32 macrocells 4064 = 64 macrocells 4128 = 128 macrocells 4256 = 256 macrocells lc xxxx xx ?xx xx xxx x xx production status blank = final production device es = engineering samples power ze = zero power, enhanced speed 4 = 4.4ns (4032ze only) 4 = 4.7ns (4064ze only) 5 = 5.8ns (all devices) 7 = 7.5ns (all devices) pin/ball count 48 (1.0 mm thickness) 64 100 132 144 package tn = lead-free tqfp mn = lead-free csbga (0.5 mm pitch) umn = lead-free ucbga (0.4 mm pitch) operating temperature range c = commercial i = industrial device family lc4128ze 5tn100c-7i datecode ispmach lc4128ze 7tn100c datecode dual mark single mark ispmach lc4032ze 5mn-7i datecode ispmach lc4032ze 7mn datecode dual mark single mark ispmach
lattice semiconductor ispmach 4000ze family data sheet 58 figure 20. mark format for 64 ucbga and 132 ucbga packages lead-free packaging commercial devices device part number macrocells voltage t pd package pin/ball count i/o grade lc4032ze LC4032ZE-4TN48C 32 1.8 4.4 lead-free tqfp 48 32 c lc4032ze-5tn48c 32 1.8 5.8 lead-free tqfp 48 32 c lc4032ze-7tn48c 32 1.8 7.5 lead-free tqfp 48 32 c lc4032ze-4mn64c 32 1.8 4.4 lead-free csbga 64 32 c lc4032ze-5mn64c 32 1.8 5.8 lead-free csbga 64 32 c lc4032ze-7mn64c 32 1.8 7.5 lead-free csbga 64 32 c lc4064ze lc4064ze-4tn48c 64 1.8 4.7 lead-free tqfp 48 32 c lc4064ze-5tn48c 64 1.8 5.8 lead-free tqfp 48 32 c lc4064ze-7tn48c 64 1.8 7.5 lead-free tqfp 48 32 c lc4064ze-4tn100c 64 1.8 4.7 lead-free tqfp 100 64 c lc4064ze-5tn100c 64 1.8 5.8 lead-free tqfp 100 64 c lc4064ze-7tn100c 64 1.8 7.5 lead-free tqfp 100 64 c lc4064ze-4mn64c 64 1.8 4.7 lead-free csbga 64 48 c lc4064ze-5mn64c 64 1.8 5.8 lead-free csbga 64 48 c lc4064ze-7mn64c 64 1.8 7.5 lead-free csbga 64 48 c lc4064ze-4umn64c 64 1.8 4.7 lead-free ucbga 64 48 c lc4064ze-5umn64c 64 1.8 5.8 lead-free ucbga 64 48 c lc4064ze-7umn64c 64 1.8 7.5 lead-free ucbga 64 48 c lc4064ze-4mn144c 64 1.8 4.7 lead-free csbga 144 64 c lc4064ze-5mn144c 64 1.8 5.8 lead-free csbga 144 64 c lc4064ze-7mn144c 64 1.8 7.5 lead-free csbga 144 64 c lc4128ze lc4128ze-5tn100c 128 1.8 5.8 lead-free tqfp 100 64 c lc4128ze-7tn100c 128 1.8 7.5 lead-free tqfp 100 64 c lc4128ze-5tn144c 128 1.8 5.8 lead-free tqfp 144 96 c lc4128ze-7tn144c 128 1.8 7.5 lead-free tqfp 144 96 c lc4128ze-5umn132c 128 1.8 5.8 lead-free ucbga 132 96 c lc4128ze-7umn132c 128 1.8 7.5 lead-free ucbga 132 96 c lc4128ze-5mn144c 128 1.8 5.8 lead-free csbga 144 96 c lc4128ze-7mn144c 128 1.8 7.5 lead-free csbga 144 96 c lc4064ze 4un-5i datecode ispmach lc4128ze 7un datecode dual mark single mark ispmach
lattice semiconductor ispmach 4000ze family data sheet 59 industrial for further information in addition to this data sheet, the following technical notes may be helpful when designing with the ispmach 4000ze family: tn1168, ispma ch 4000ze timing model design and usage guidelines tn1174, adv anced f eatures of the ispma ch 4000ze f amily tn1187, p o w er estimation in ispma ch 4000ze de vices technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com lc4256ze lc4256ze-5tn100c 256 1.8 5.8 lead-free tqfp 100 64 c lc4256ze-7tn100c 256 1.8 7.5 lead-free tqfp 100 64 c lc4256ze-5tn144c 256 1.8 5.8 lead-free tqfp 144 96 c lc4256ze-7tn144c 256 1.8 7.5 lead-free tqfp 144 96 c lc4256ze-5mn144c 256 1.8 5.8 lead-free csbga 144 108 c lc4256ze-7mn144c 256 1.8 7.5 lead-free csbga 144 108 c device part number macrocells voltage t pd package pin/ball count i/o grade lc4032ze lc4032ze-5tn48i 32 1.8 5.8 lead-free tqfp 48 32 i lc4032ze-7tn48i 32 1.8 7.5 lead-free tqfp 48 32 i lc4032ze-5mn64i 32 1.8 5.8 lead-free csbga 64 32 i lc4032ze-7mn64i 32 1.8 7.5 lead-free csbga 64 32 i lc4064ze lc4064ze-5tn48i 64 1.8 5.8 lead-free tqfp 48 32 i lc4064ze-7tn48i 64 1.8 7.5 lead-free tqfp 48 32 i lc4064ze-5tn100i 64 1.8 5.8 lead-free tqfp 100 64 i lc4064ze-7tn100i 64 1.8 7.5 lead-free tqfp 100 64 i lc4064ze-5mn64i 64 1.8 5.8 lead-free csbga 64 48 i lc4064ze-7mn64i 64 1.8 7.5 lead-free csbga 64 48 i lc4064ze-5umn64i 64 1.8 5.8 lead-free ucbga 64 48 i lc4064ze-7umn64i 64 1.8 7.5 lead-free ucbga 64 48 i lc4064ze-5mn144i 64 1.8 5.8 lead-free csbga 144 64 i lc4064ze-7mn144i 64 1.8 7.5 lead-free csbga 144 64 i lc4128ze lc4128ze-7tn100i 128 1.8 7.5 lead-free tqfp 100 64 i lc4128ze-7umn132i 128 1.8 7.5 lead-free ucbga 132 96 i lc4128ze-7tn144i 128 1.8 7.5 lead-free tqfp 144 96 i lc4128ze-7mn144i 128 1.8 7.5 lead-free csbga 144 96 i lc4256ze lc4256ze-7tn100i 256 1.8 7.5 lead-free tqfp 100 64 i lc4256ze-7tn144i 256 1.8 7.5 lead-free tqfp 144 96 i lc4256ze-7mn144i 256 1.8 7.5 lead-free csbga 144 108 i commercial devices (cont.) device part number macrocells voltage t pd package pin/ball count i/o grade
lattice semiconductor ispmach 4000ze family data sheet 60 revision history date version change summary april 2008 01.0 initial release. july 2008 01.1 updated features bullets. updated typical hysteresis voltage. updated power guard for dedicated inputs section. updated dc electrical characteristics table. updated supply current table. updated i/o dc electrical characteristics table and note 2. updated ispmach 4000ze timing model. added new parameters for the internal oscillator. updated orp reference table. updated power supply and nc connections table. updated 100 tqfp logic signal connections table with lc4128ze and 4256ze. updated 144 csbga logic signal connections table with lc4128ze and 4256ze. added 144 tqfp logic signal connections table. august 2008 01.2 data sheet status changed from advance to ?al. updated supply current table. updated external switching characteristics. updated internal timing parameters. updated power consumption graph and power estimation coef?ients table. updated ordering information mark format example. december 2008 01.3 updated ispmach 4000ze family selection guide table to include 64-ball ucbga and 132-ball ucbga packages. updated ispmach 4000ze power supply and nc connections table to include 64-ball ucbga and 132-ball ucbga packages. added logic signal connections tables for 64-ball ucbga and 132-ball ucbga packages. updated part number description diagram for 64-ball ucbga and 132-ball ucbga packages. updated ordering information tables for 64-ball ucbga and 132-ball ucbga packages. may 2009 01.4 correction to t cw , tgw, t wir and f max parameters in external switching characteristics table.

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